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| 85310ayi-31 www.icst.com/products/hiperclocks.html rev. e april 11, 2007 1 integrated circuit systems, inc. ics85310i-31 l ow s kew , d ual , 1- to -5 2.5v/3.3v d ifferential - to -ecl/lvpecl f anout b uffer g eneral d escription the ics85310i-31 is a low skew, high performance dual 1-to-5 differential-to-2.5v/3.3v ecl/lvpecl fanout buffer and a member of the hiperclocks? family of high performance clock solutions from ics. the clkx, nclkx pairs can accept most standard differential input levels. the ics85310i-31 is charac- terized to operate from either a 2.5v or a 3.3v power supply. guaranteed output and part-to-part skew characteristics make the ics85310i-31 ideal for those clock distribution applications demanding well defined performance and repeatability. b lock d iagram p in a ssignment hiperclocks? ic s 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 qa3 nqa3 qa4 nqa4 qb0 nqb0 qb1 nqb1 v cc clk_ena clka nclka clk_enb clkb nclkb v ee v cco qb2 nqb2 qb3 nqb3 qb4 nqb4 v cco v cco nqa2 qa2 nqa1 qa1 nqa0 qa0 v cco 32-lead lqfp 7mm x 7mm x 1.4mm package body y package top view ics85310i-31 qa0 nqa0 qa1 nqa1 qa2 nqa2 qa3 nqa3 qa4 nqa4 clka nclka clk_ena d q le qb0 nqb0 qb1 nqb1 qb2 nqb2 qb3 nqb3 qb4 nqb4 clkb nclkb clk_enb d q le f eatures ? two differential 2.5v/3.3v lvpecl / ecl bank outputs ? two differential clock input pairs ? clkx, nclkx pairs can accept the following differential input levels: lvpecl, lvds, lvhstl, sstl, hcsl ? maximum output frequency: 700mhz ? translates any single ended input signal to 3.3v lvpecl levels with resistor bias on nclkx input ? output skew: 25ps (typical) ? part-to-part skew: 270ps (typical) ? propagation delay: 1.7ns (typical) ? additive phase jitter, rms: <0.13ps (typical) ? lvpecl mode operating voltage supply range: v cc = 2.375v to 3.8v, v ee = 0v ? ecl mode operating voltage supply range: v cc = 0v, v ee = -3.8v to -2.375v ? -40c to 85c ambient operating temperature ? lead-free package fully rohs compliant
85310ayi-31 www.icst.com/products/hiperclocks.html rev. e april 11, 2007 2 integrated circuit systems, inc. ics85310i-31 l ow s kew , d ual , 1- to -5 2.5v/3.3v d ifferential - to -ecl/lvpecl f anout b uffer t able 1. p in d escriptions t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d 1v c c r e w o p. n i p y l p p u s e r o c 2a n e _ k l cd e s u n up u l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . e l b a n e k c o l c g n i z i n o r h c n y s 3a k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 4a k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 5b n e _ k l cd e s u n up u l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . e l b a n e k c o l c g n i z i n o r h c n y s 6b k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 7b k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 8v e e r e w o p. n i p y l p p u s e v i t a g e n 2 3 , 5 2 , 6 1 , 9v o c c r e w o p. s n i p y l p p u s t u p t u o 1 1 , 0 14 b q , 4 b q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 3 1 , 2 13 b q , 3 b q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 5 1 , 4 12 b q , 2 b q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 8 1 , 7 11 b q , 1 b q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 0 2 , 9 10 b q , 0 b q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 2 2 , 1 24 a q , 4 a q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 4 2 , 3 23 a q , 3 a q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 7 2 , 6 22 a q , 2 a q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 9 2 , 8 21 a q , 1 a q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d 1 3 , 0 30 a q , 0 a q nt u p t u o. s l e v e l e c a f r e t n i l c e p v l . r i a p t u p t u o l a i t n e r e f f i d : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k 85310ayi-31 www.icst.com/products/hiperclocks.html rev. e april 11, 2007 3 integrated circuit systems, inc. ics85310i-31 l ow s kew , d ual , 1- to -5 2.5v/3.3v d ifferential - to -ecl/lvpecl f anout b uffer t able 3a. c ontrol i nput f unction t able t able 3b. c lock i nput f unction t able s t u p n is t u p t u o b n e _ k l c , a n e _ k l c4 b q : 0 b q , 4 a q : 0 a q4 b q n : 0 b q n , 4 a q n : 0 a q n 0w o l ; d e l b a s i dh g i h ; d e l b a s i d 1d e l b a n ed e l b a n e e g d e k c o l c t u p n i g n i l l a f d n a g n i s i r a g n i w o l l o f d e l b a n e r o d e l b a s i d e r a s t u p t u o k c o l c e h t , s e h c t i w s n e _ k l c r e t f a . 1 e r u g i f n i n w o h s s a d e b i r c s e d s a s t u p n i b k l c n , b k l c d n a a k l c n , a k l c e h t f o n o i t c n u f a e r a s t u p t u o e h t f o e t a t s e h t , e d o m e v i t c a e h t n i . b 3 e l b a t n i s t u p n is t u p t u o e d o m t u p t u o o t t u p n iy t i r a l o p b k l c r o a k l cb k l c n r o a k l c n , 4 a q : 0 a q 4 b q : 0 b q , 4 a q n : 0 a q n 4 b q n : 0 b q n 01w o lh g i hl a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 10 h g i hw o ll a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 01 e t o n ; d e s a i bw o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 11 e t o n ; d e s a i bh g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 1 e t o n ; d e s a i b0h g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i 1 e t o n ; d e s a i b1w o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i . " s l e v e l d e d n e e l g n i s t p e c c a o t t u p n i l a i t n e r e f f i d e h t g n i r i w " n o i t a m r o f n i n o i t a c i l p p a e h t o t r e f e r e s a e l p : 1 e t o n f igure 1. clk_en t iming d iagram enabled disabled clka, nclkb clka, clkb clk_ena, clk_enb nqa0:nqa4, nqb0:nqb4 qa0:qa4, qb0:qb4 85310ayi-31 www.icst.com/products/hiperclocks.html rev. e april 11, 2007 4 integrated circuit systems, inc. ics85310i-31 l ow s kew , d ual , 1- to -5 2.5v/3.3v d ifferential - to -ecl/lvpecl f anout b uffer t able 4a. p ower s upply dc c haracteristics , v cc , v cco = 2.375v to 3.8v, t a = -40c to 85c t able 4c. d ifferential dc c haracteristics , v cc , v cco = 2.375v to 3.8v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v c c e g a t l o v y l p p u s e r o c 5 7 3 . 23 . 38 . 3v v o c c e g a t l o v y l p p u s t u p t u o 5 7 3 . 23 . 38 . 3v i e e t n e r r u c y l p p u s r e w o p 0 2 1a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i b k l c , a k l cv c c v = n i v 8 . 3 =0 5 1a b k l c n , a k l c nv c c v = n i v 8 . 3 =5a i l i t n e r r u c w o l t u p n i b k l c , a k l cv c c v , v 8 . 3 = n i v 0 =5 -a b k l c n , a k l c nv c c v , v 8 . 3 = n i v 0 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o cv e e 5 . 0 +v c c 5 8 . 0 -v v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i . v s i b k l c n , b k l c d n a a k l c n , a k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n c c . v 3 . 0 + t able 4b. lvcmos / lvttl dc c haracteristics , v cc , v cco = 2.375v to 3.8v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n ib n e _ k l c , a n e _ k l c2v c c 3 . 0 +v v l i e g a t l o v w o l t u p n ib n e _ k l c , a n e _ k l c3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n ib n e _ k l c , a n e _ k l cv c c v = n i v 8 . 3 =5a i l i t n e r r u c w o l t u p n ib n e _ k l c , a n e _ k l cv c c v , v 8 . 3 = n i v 0 =0 5 1 -a note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 47.9c/w (0 lfpm) storage temperature, t stg -65c to 150c 85310ayi-31 www.icst.com/products/hiperclocks.html rev. e april 11, 2007 5 integrated circuit systems, inc. ics85310i-31 l ow s kew , d ual , 1- to -5 2.5v/3.3v d ifferential - to -ecl/lvpecl f anout b uffer t able 5. ac c haracteristics , v cc , v cco = 2.375v to 3.8v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 0 7z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p? z h m 0 0 57 . 12 . 2s n t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o 5 20 5s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p 0 7 20 5 5s p t t i j ; s m r , r e t t i j e s a h p e v i t i d d a r e f f u b n o i t c e s r e t t i j e s a h p e v i t i d d a o t r e f e r 3 1 . 0 85310ayi-31 www.icst.com/products/hiperclocks.html rev. e april 11, 2007 7 integrated circuit systems, inc. ics85310i-31 l ow s kew , d ual , 1- to -5 2.5v/3.3v d ifferential - to -ecl/lvpecl f anout b uffer p arameter m easurement i nformation 3.3v o utput l oad ac t est c ircuit d ifferential i nput l evel o utput s kew p art - to -p art s kew o utput d uty c ycle /p ulse w idth /p eriod o utput r ise /f all t ime p ropagation d elay v cmr cross points v pp v ee nclka, nclkb v cc clka, clkb scope qx nqx lvpecl 2v -1.8v to -0.375v t sk(pp) t sk(o) nqx qx nqy qy pa r t 1 pa r t 2 nqx qx nqy qy clock outputs 20% 80% 80% 20% t r t f v sw i n g t pd nclka, nclkb qax, qbx nqax, nqbx clka, clkb t pw t period t pw t period odc = x 100% qa0:qa4, qb0:qb4 nqa0:nqa4, nqb0:nqb4 v ee v cc , v cco 85310ayi-31 www.icst.com/products/hiperclocks.html rev. e april 11, 2007 8 integrated circuit systems, inc. ics85310i-31 l ow s kew , d ual , 1- to -5 2.5v/3.3v d ifferential - to -ecl/lvpecl f anout b uffer a pplication i nformation f igure 2. s ingle e nded s ignal d riving d ifferential i nput v cc - 2v 50 50 rtt z o = 50 z o = 50 fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 125 84 84 z o = 50 z o = 50 fout fin t ermination for 3.3v lvpecl o utputs the clock layout topology shown below is a typical termina- tion for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that gen- erate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock lay- outs may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. f igure 3b. lvpecl o utput t ermination f igure 3a. lvpecl o utput t ermination figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clkx nclkx vcc 85310ayi-31 www.icst.com/products/hiperclocks.html rev. e april 11, 2007 9 integrated circuit systems, inc. ics85310i-31 l ow s kew , d ual , 1- to -5 2.5v/3.3v d ifferential - to -ecl/lvpecl f anout b uffer t ermination for 2.5v lvpecl o utputs figure 4a and figure 4b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminat- ing 50 to v cc - 2v. for v cc = 2.5v, the v cc - 2v is very close to ground level. the r3 in figure 4b can be eliminated and the termination is shown in figure 4c. f igure 4c. 2.5v lvpecl t ermination e xample r2 50 zo = 50 ohm vcco=2.5v r1 50 zo = 50 ohm + - 2.5v 2,5v lvpecl driv er f igure 4b. 2.5v lvpecl d river t ermination e xample vcco=2.5v r1 50 r2 50 zo = 50 ohm r3 18 2,5v lvpecl driv er zo = 50 ohm + - 2.5v f igure 4a. 2.5v lvpecl d river t ermination e xample r2 62.5 2.5v 2,5v lvpecl driv er r3 250 zo = 50 ohm zo = 50 ohm r4 62.5 2.5v + - r1 250 vcco=2.5v 85310ayi-31 www.icst.com/products/hiperclocks.html rev. e april 11, 2007 10 integrated circuit systems, inc. ics85310i-31 l ow s kew , d ual , 1- to -5 2.5v/3.3v d ifferential - to -ecl/lvpecl f anout b uffer f igure 5c. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 5b. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river f igure 5d. h i p er c lock s clk/nclk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 5a to 5e show inter- face examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested f igure 5a. h i p er c lock s clk/nclk i nput d riven by ics h i p er c lock s lvhstl d river here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 5a, the input termination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 5e. h i p er c lock s clk/nclk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1 zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v 85310ayi-31 www.icst.com/products/hiperclocks.html rev. e april 11, 2007 11 integrated circuit systems, inc. ics85310i-31 l ow s kew , d ual , 1- to -5 2.5v/3.3v d ifferential - to -ecl/lvpecl f anout b uffer ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics85310i-31. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics85310i-31 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.8v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.8v * 120ma = 456mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 10 * 30mw = 300mw total power _max (3.8v, with all outputs switching) = 456mw + 300mw = 756mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature i n order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.756w * 42.1c/w = 116.8c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). t able 6. t hermal r esistance ja for 32- pin lqfp, f orced c onvection 85310ayi-31 www.icst.com/products/hiperclocks.html rev. e april 11, 2007 12 integrated circuit systems, inc. ics85310i-31 l ow s kew , d ual , 1- to -5 2.5v/3.3v d ifferential - to -ecl/lvpecl f anout b uffer 3. calculations and equations. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco - 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h = [(v oh_max ? (v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco _max - v oh_max )) /r l ] * (v cco _max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco _max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 6. lvpecl driver circuit and termination q1 v out v cco rl 50 v cco - 2v 85310ayi-31 www.icst.com/products/hiperclocks.html rev. e april 11, 2007 13 integrated circuit systems, inc. ics85310i-31 l ow s kew , d ual , 1- to -5 2.5v/3.3v d ifferential - to -ecl/lvpecl f anout b uffer r eliability i nformation t ransistor c ount the transistor count for ics85310i-31 is: 1216 t able 7. ja vs . a ir f low t able for 32 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55. 9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42. 1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. 85310ayi-31 www.icst.com/products/hiperclocks.html rev. e april 11, 2007 14 integrated circuit systems, inc. ics85310i-31 l ow s kew , d ual , 1- to -5 2.5v/3.3v d ifferential - to -ecl/lvpecl f anout b uffer p ackage o utline - y s uffix for 32 l ead lqfp t able 8. p ackage d imensions reference document: jedec publication 95, ms-026 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i ml a n i m o nm u m i x a m n 2 3 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 0 3 . 07 3 . 05 4 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -0 1 . 0 85310ayi-31 www.icst.com/products/hiperclocks.html rev. e april 11, 2007 15 integrated circuit systems, inc. ics85310i-31 l ow s kew , d ual , 1- to -5 2.5v/3.3v d ifferential - to -ecl/lvpecl f anout b uffer t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability, or other ext raordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 1 3 - i y a 0 1 3 5 8 s c i1 3 i y a 0 1 3 5 8 s c ip f q l d a e l 2 3y a r tc 5 8 o t c 0 4 - t 1 3 - i y a 0 1 3 5 8 s c i1 3 i y a 0 1 3 5 8 s c ip f q l d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - f l 1 3 - i y a 0 1 3 5 8 s c il 1 3 i a 0 1 3 5 s c ip f q l " e e r f d a e l " d a e l 2 3y a r tc 5 8 o t c 0 4 - t f l 1 3 - i y a 0 1 3 5 8 s c il 1 3 i a 0 1 3 5 s c ip f q l " e e r f d a e l " d a e l 2 3l e e r & e p a t 0 0 0 1c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n the aforementioned trademark, hiperclocks is a trademark of integrated circuit systems, inc. or its subsidiaries in the united states and/or other countries. 85310ayi-31 www.icst.com/products/hiperclocks.html rev. e april 11, 2007 16 integrated circuit systems, inc. ics85310i-31 l ow s kew , d ual , 1- to -5 2.5v/3.3v d ifferential - to -ecl/lvpecl f anout b uffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a9 . s t u p t u o l c e p v l r o f n o i t a n i m r e t d e d d a 2 0 / 0 3 / 5 a 0 1 3 5 8 s c i o t 1 3 - 0 1 3 5 8 s c i m o r f r e b m u n t r a p d e t a d p uia t a d e h t t u o h g u o r h t 1 3 - . e r u t a r e p m e t g n i t a r e p o t c e l f e r o t t e e h s 2 0 / 4 2 / 7 a9 t4 1. 1 3 i y a 0 1 3 5 8 s c i o t 1 3 - i y a 0 1 3 5 8 s c i m o r f g n i k r a m d e t c e r r o c 2 0 / 5 2 / 7 b a 4 t4 0 1 i r o f e u l a v . x a m d e s a e r c n i - e l b a t y l p p u s r e w o p e e . x a m a m 0 3 m o r f a m 0 2 1 o t i d e s a e r c n i e h t o t d e t s u j d a - e r e v a h s n o i t a r e d i s n o c r e w o p e e . e u l a v 2 0 / 3 2 / 0 1 c 2 t d 4 t 2 4 5 9 & 8 1 1 & 0 1 4 1 . l a c i p y t f p 4 o t . x a m f p 4 d e g n a h c - e l b a t s c i t s i r e t c a r a h c n i p . s g n i t a r m u m i x a m e t u l o s b a d e t a d p u v d e g n a h c - e l b a t s c i t s i r e t c a r a h c c d l c e p v l g n i w s . x a m v 0 . 1 o t . x a m v 5 8 . 0 m o r f , d e d d a n o i t c e s n o i t a c i l p p a s t u p t u o l c e p v l v 5 . 2 r o f n o i t a n i m r e t d n a . e c a f r e t n i t u p n i k c o l c l a i t n e r e f f i d . v 8 . 3 r o f n o i t a p i s s i d r e w o p l a t o t d e t a l u c l a c e r - s n o i t a r e d i s n o c r e w o p o t 1 3 i y a 0 1 3 5 8 s c i m o r f g n i k r a m d e t c e r r o c - e l b a t n o i t a m r o f n i g n i r e d r o . 1 3 - i a 0 1 3 5 8 s c i 3 0 / 1 3 / 7 d 5 t 9 t 1 5 6 4 1 . t e l l u b e e r f - d a e l d n a t e l l u b r e t t i j e s a h p e v i t i d d a d e d d a - n o i t c e s s e r u t a e f . w o r r e t t i j e s a h p e v i t i d d a d e d d a - e l b a t s c i t s i r e t c a r a h c c a . n o i t c e s r e t t i j e s a h p e v i t i d d a d e d d a . e t o n d n a r e b m u n t r a p e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 5 0 / 6 / 7 e d 4 t5 1 1 - 0 1 - e l b a t s c i t s i r e t c a r a h c c d l c e p v lv d e t c e r r o c h o v m o r f . x a m o c c v o t v 0 . 1 - o c c - . v 9 . 0 v t c e l f e r o t n o i t a p i s s i d r e w o p d e t c e r r o c - s n o i t a r e d i s n o c r e w o p h o e l b a t n i x a m . d 4 7 0 / 1 1 / 4 |
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